1. Field of the Invention
The present invention relates to an organic thin film transistor, a method of producing the same, and a shadow mask used in the method, and more particularly, to a plurality of organic thin film transistors disposed on a substrate in a matrix-shape to make an active matrix display, a method of producing the same, and a shadow mask used in the method.
2. Discussion of the Background
An organic thin film transistor (OTFT) includes an organic material, which acts as a channel between a source electrode and a drain electrode, whereby the conductivity of the organic material is controlled by a gate electrode of the OTFT.
In several applications, such as in an Active Matrix Display, a plurality of OTFTs are arranged in a series of vertical and horizontal lines, thereby forming a matrix. When manufacturing OTFTs arranged in a matrix, the OTFTs are structured by depositing an array of semiconductor areas, which act as channels and which overlap the drain electrodes and source electrodes. The organic semiconductor material is deposited onto the OTFT substrate, which already includes the drain electrodes and source electrodes, by using thermal evaporation of organic semiconductor materials through a shadow mask or by using solution based processes for semiconductor materials, like printing techniques such as inkjet printing, a printing process sold under the trademark Flexo®, doctor blade coating, or other technologies.
The patterning of the semiconductor layer is essential for achieving a good single transistor performance, such as a high ON/OFF current ratio. The patterning is also required to prevent unwanted cross-talk effects between adjacent TFTs and conductive lines in an electronic circuit. The non-patterned semiconductor element can cause a current leakage path. Therefore, the semiconductor element has to be deposited only in the channel area of a single transistor where no contact with the channel area of adjacent TFTs shall occur.
WO 03/098696 A1 (Seiko Epson) describes the fabrication of circuit inter-connections in thin film circuits involving the use of a lithographic technique to provide patterned layer and depositing first material at localized regions using inkjet printing technique.
EP 1 139 455 A2 (Seiko Epson) describes a method of manufacturing an organic electroluminescent (EL) element. A special patterning is required to create an opening corresponding to the region for the formation of a constitutive layer.
US 2003/0059975 A1 and WO 01/46987 A2 (Plastic Logic) describe a method of forming at least one part of an integrated circuit by ink-jet printing.
WO 03/056641 A1 (Plastic Logic) describes a method of forming an organic or partly organic switching device. The method includes depositing layers of conducting, semiconducting and/or insulating layers by solution processing and direct printing, and defining high-resolution patterns of electro-active polymers by self-aligned formation of a surface energy barrier around a first pattern that repels the solution of a second material.
DE 100 61 297 A1 (Siemens) describes an organic field-effect transistor (OFET), a method of structuring an OFET, and an integrated circuit with improved structuring of the functional polymer layers. The improved structuring is obtained by introducing, using a doctor blade, a functional polymer in a mold layer into which recesses are initially produced through an additional fabrication step, such as imprinting.
U.S. Pat. No. 5,946,551 (Dimitrakopoulos et al.) describes the fabrication of TFTs with organic semiconductors, where shadow mask techniques are used to define source/drain metal electrodes.
U.S. Pat. No. 6,667,215 B2 (3M) describes a method of manufacturing transistors by using stationary shadow masks to define source and drain electrodes.
U.S. Pat. No. 6,384,529 B2 (Kodak) describes a color active matrix organic electro-luminescent display with an integrated shadow mask. The shadow masks are used to define the color conversion layers or the emissive RGB sub pixels.
U.S. Pat. No. 5,742,129 (Pioneer) describes a method of manufacturing an organic EL display panel having a plurality of emitting portions surrounded by ramparts and arranged as a matrix. In the method, the shadow mask is used to deposit the media. However, there is a repeated putting and aligning step required to deposit the media through the openings of the shadow mask.
Therefore, all techniques for the deposition of the semiconductor known in the state of the art require a very precise alignment procedure. Where a shadow mask technique is used, the shadow mask must be very precisely aligned with the substrate. With a photolithographic patterned semiconductor, the photomask has to be precisely aligned as well. Also, all printing techniques for the deposition of the semiconductor known in the state of the art require a very precise alignment procedure between a printing device and a substrate to be printed. Additionally, printing processes for flexible substrates require cost-intensive local registration during the printing process due to a possible shrinkage or deflection of the substrate.
FIG. 1 shows a sectional view of a bottom gate OTFT which can be used, for example, in an active matrix OLED. The OTFT includes a gate electrode 4, which is disposed on a substrate 5, an insulator 3, a source electrode 2 and a drain electrode 2a, whereby a semiconducting element 1 is disposed between the source electrode 2 and the drain electrode 2a, thereby forming a semiconducting channel 11.
FIG. 2 shows a sectional view of a top gate OTFT which can be used, for example, in an active matrix OLED. The OTFT comprises a source electrode 2 and a drain electrode 2a, which are disposed on a substrate 5, whereby semiconducting element 1 is disposed between the source electrode 2 and the drain electrode 2a, thereby forming a semiconducting channel 11. An insulator 3 and a gate electrode 4 are disposed upon the electrodes 2 and 2a and the channel 11.
FIG. 3A and FIG. 4A show the basic principle of the deposition of organic semiconductor element 1 through a shadow mask 13 for the manufacture of a bottom (shown in FIG. 3A) or a top (shown in FIG. 4A) gate OTFT. An evaporation stream 8 is controlled by the openings in the shadow mask 13, thereby resulting in a deposition of a semiconductor element 1 at a predetermined area between the source electrode 2 and the drain electrode 2a. A continuous deposition of the semiconductor element 1 is not possible because connections between adjacent TFTs are generally avoided. Therefore high alignment tolerances for the position of the shadow mask 13 in relation to the substrate 5 exist in order to deposit the semiconductor element 1 substantially between only the source electrode 2 and drain electrode 2a. 
FIG. 3B and FIG. 4B show the basic principle of the deposition of organic semiconductor element 1 by inkjet printing for the manufacture of a bottom (shown in FIG. 3B) or a top (shown in FIG. 4B) gate OTFT in a sectional view. The application of semiconductor ink droplets 15 is controlled by a print head 14, thereby resulting in a deposition of semiconductor element 1 at a predetermined area between the source electrode 2 and the drain electrode 2a. A continuous deposition of semiconductor element 1 is not possible because connections between adjacent TFTs are generally avoided. Therefore high alignment tolerances for the position of the print head 14 in relation to the substrate 5 exist to deposit the semiconductor element 1 substantially between only the source electrode 2 and the drain electrode 2a. 
FIG. 5 shows a top view of a conventional organic TFT architecture including the source electrode 2 and the drain electrode 2a formed on the insulator 3, and the semiconductor channel 11 connecting the source electrode 2 and the drain electrode 2a. The openings of a shadow mask (not shown) have to be precisely positioned over the gaps between the source electrodes 2 and the drain electrodes 2a for the deposition of the semiconductor element 1. The precision is usually in the sub-mm range and, for active matrix OLED with high resolution, in the μm range. The channel 11 to be filled with the semiconductor element 1 comprises a channel Length 16 (L) of the transistor, which approximately equals the distance between the drain and source electrodes, and a channel Width 17 (W) of the transistor.